CSP (Chip Size Package) semiconductor devices have been popularly used to meet the demand for compact electronics and automated manufacturing processes.
FIG. 11 shows the cross-sectional structure of a conventional CSP semiconductor device 100 as an example. The CSP semiconductor device 100 has gold wires 103 extending from electrode pads 102 formed along the periphery of a semiconductor chip 101. Through the gold wires 103, the semiconductor chip 101 is electrically connected to an interposer substrate, or circuit board, 104. The CSP semiconductor device 100 has also external lead electrodes 105 formed on the back of the interposer substrate 104, via which electrodes 105 the interposer substrate 104 is connected to an external device (not shown in the figure).
The wire bonding by means of the gold wires 103 electrically connects the electrode pads 102 on the semiconductor chip 101 to the interposer substrate 104. The gold wires 103 add an extra height to the device 100. They also need be sealed by molding resin 106 for protection. These factors present difficulties in reducing the thickness of the CSP semiconductor device 100.
FCB (Flip Chip Bonding) semiconductor devices like the one shown in FIG. 12(a) and those with through electrodes like the one shown in FIG. 12(b) offer solutions to these problems. These types of CSP semiconductor devices eliminate the need for wires, thereby allowing for thinner devices.
In the FCB semiconductor device 200 in FIG. 12(a), a semiconductor chip 201 is electrically connected to contact pads 205 on an interposer substrate 204 via protrusion electrodes 203 formed on electrode pads 202. The semiconductor chip 201 is positioned so that its surface 206 on which circuitry is formed is opposite to the interposer substrate 204. Sealing resin 207 resides between the surface 206 and the interposer substrate 204 to provide protection to the semiconductor chip 201 and the connecting parts.
In the semiconductor device 210 in FIG. 12(b) where electrical connections are provided by means of through electrodes, protrusion electrodes 215 electrically connect through electrodes 212 formed on a semiconductor chip 211 to contact pads 214 formed on an interposer substrate 213. Sealing resin 216 may be injected for sealing between the semiconductor chip 211 and the interposer substrate 213 if necessary; when this is the case, circuitry is formed on the upper surface 217 of the semiconductor chip 211.
Japanese Published Unexamined Patent Application 10-223833 (Tokukaihei 10-223833/1998; published on Aug. 21, 1998), Japanese Patent 3186941 (issued on May 11, 2001), U.S. Pat. No. 6,184,060 (Date of patent: Feb. 6, 2001), and other recent documents disclose proposed multi-chip semiconductor devices in which the foregoing semiconductor device includes film carrier semiconductor modules which are stacked vertically on top of each other and connected electrically for greater packaging efficiency.
Referring to FIG. 13, a multi-chip semiconductor device 300 described in Tokukaihei 10-223833/1998 includes three chips 301a, 301b, 301c stacked sequentially upwards from bottom. Each chip 301a, 301b, 301c is principally made up of a silicon substrate 302 carrying integrated devices; wiring layers 303 connecting the integrated devices in a predetermined pattern; through electrodes (connection plugs) 306 provided inside through holes 305 extending through the silicon substrate 302 and an interlayer insulating film 304 for the wiring layers 303 to electrically connect the chips 301a, 301b to the chips 301b, 301c; and an opening insulating film 307. The through electrodes 306 provide external connection terminals for grounding and power and various signal supplies, and are formed in accordance with uses for each chip 301a, 301b, 301c. The back of the silicon substrate 302, except for the openings for the through electrodes 306, is covered with a back insulating film 308.
Through the wiring layers 303 on the chip 301a, 301b, 301c are there provided electrode pads 309 electrically connected to the metal plugs 306. The through electrode 306 for the chip 301a is connected to the through electrode 306 for the chip 301b via an electrode pad 309 and a solder bump 310; meanwhile, the through electrode 306 for the chip 301b is connected to the through electrode 306 for the semiconductor device 301c via another electrode pad 309 and another solder bump 310.
Thus, the chips 301a, 301b, 301c are electrically connected with each other, offering a chip-stack semiconductor device.
In the conventional chip-stack semiconductor device, the terminal for the same signal is disposed at the same position on every chip, to provide electrical connections between the vertically stacked chips.
However, in the conventional chip-stack semiconductor device with through electrodes, all the through electrodes have equal cross-sectional areas of which the value is determined disregarding the functions of the through electrodes: e.g., the ground and power supply terminals have equal cross-sectional areas to those of the signal terminals despite the former conducting greater electric current than the latter. This raises problems that those terminals which need pass great electric current may heat up, delay signals, or develop other undesirable phenomena.
Further, in stacking chips with through electrodes, a chip adds an extra length to the through electrode connecting the top and the bottom chips. The extra length of the electrode translates into an extra resistance, resulting in voltage drop, heating, delay, and loss.
Further, the through electrodes vary greatly in interconnect line length, hence in resistance.